Rianta offers IP Cores and Verification IP for Ethernet, Security and Deep Learning Acceleration. We focus on delivering complete IP blocks for Datacenter Infrastructure, Communications Infrastructure (e.g. 5G backhaul), and Automotive Networking applications.

Our Engineering Design and Verification Services teams understand the complexity of using 3rd party IP and know the challenges customers face when integrating, modifying, verifying, and testing IP that was packaged without a deep knowledge of customer requirements. 

ASIC / SoC IP Cores : Ethernet MAC/PCS, Security, AI Acceleration Product Families
Ethernet	Security	Deep Learning Acceleration

Rianta specializes in reusable RTL-based IP cores that are configured to specific semiconductor technology nodes. We partner with you to integrate the verified Design IP core into your platform. We develop and license IP that can be ported into most processes and geometries; leveraging the experience we gained after numerous successful ASIC/ASSP developments and associated software and system level designs.

To inquire about our IP Products please email info@riantasolutions.com

Product Family	Rianta IP Core Product Family	Product Number	Variants
Ethernet ASIC/SoC IP Cores	10G to 100G Single Channel Ethernet MAC/PCS IP	RSm100™	5G Comms Infrastructure Datacenter
	200G/400G Single Channel Ethernet MAC/PCS IP(NEW)	RSm400™
	1G to 200G Channelized Ethernet MAC/PCS IP	RSm200C™
	10G to 400G Channelized Ethernet MAC/PCS IP	RSm400C™
Security ASIC/SoC IP Cores	1G Channelized Ethernet MACsec IP	RS_MCS1™	Automotive 5G Comms Infrastructure Datacenter
	1G/10G Channelized Ethernet MACsec IP	RS_MCS1/10™
	1G/100G Channelized Ethernet MACsec IP	RS_MCS100™
	400G Channelized Ethernet MACsec IP (NEW)	RS_MCS400™
Deep Learning Acceleration ASIC/SoC IP Cores	Deep Learning Acceleration Family of IP Blocks	Coming Soon Contact Rianta to request a Deep Learning pre-release briefing	Datacenter Automotive 5G Comms Infrastructure

ASIC/SoC/FPGA Verification IP

We also specialize in advanced, automated testbenches with self-checking protocol monitors and generators. Using the latest UVM/OVM/VMM methodologies along with C++ and SystemVerilog languages, our testbenches and verification IP support the following:

• automated constrained random testing
• corner case stressing
• protocol compliance
• porting of verification testcases to lab validation scripts
• porting of lab and field debug cases to verification testcases