ethernet ip channelized pac pcs uvm ovm vmm systemverilog verificationRianta focuses on delivering complete IP blocks. We understand the complexity of using 3rd party IP and know the frustration customers feel when integrating, modifying, verifying, and testing IP that was packaged without a deep knowledge of customer requirements.

ASIC Design  

Rianta specializes in reusable RTL-based IP cores that are configured to specific semiconductor technology nodes. We partner with you to integrate the verified Design IP core into your platform. We develop and license IP that can be ported into most processes and geometries; leveraging the experience we gained after numerous successful ASIC/ASSP developments and associated Software and System level designs. We effectively address key wireline, wireless, and industrial applications.

Protocol Description Product Number
Ethernet 10/100/1000 Ethernet MAC/PCS RSm1110
Ethernet 10Gb/s Ethernet MAC RS1010
Ethernet 10Gb/s Ethernet PCS RS1011
Ethernet 40/100Gb/s Ethernet MAC/PCS RSm4100
Ethernet 400Gb/s Multi-rate (10-400G) Channelized MAC RSm400C
Ethernet 400Gb/s Multi-rate (10-400G) Channelized MAC with FlexE RSm400C_FE
MACsec MACsec security RS_MACsec
PCIe PCS 4.0 RS_PCIe_PCS_4

ASIC/FPGA Verification IP

We also specialize in advanced, automated testbenches with self-checking protocol monitors and generators. Using the latest UVM/OVM/VMM methodologies along with C++ and SystemVerilog languages, our testbenches and verification IP support the following:

  • automated constrained random testing
  • corner case stressing
  • protocol compliance
  • porting of verification testcases to lab validation scripts
  • porting of lab and field debug cases to verification testcases
Protocol Interfaces Methodologies Product Number
Ethernet

VIP for 1G/10/100/1G/10G/40G/100G

/200G/400G/600G

UVM, VMM, OVM SystemVerilog RSV40100
Ethernet VIP for switch with 10G - 100G Interfaces UVM, VMM, OVM SystemVerilog RSVxxxxTB
SDN VIP for SDN Switch UVM, VMM, OVM SystemVerilog RSV_SDN
FlexE VIP for FlexE with 5G granularity UVM, VMM, OVM SystemVerilog

RSV_FlexE

Memory VIP for embedded memories UVM, VMM, OVM SystemVerilog RS_MEM
IO VIP for various CPU interfaces UVM, VMM, OVM SystemVerilog RS_IO
MACsec VIP for MACsec (100G) UVM, VMM, OVM SystemVerilog RSV_MACsec

IP Integration 

With our turnkey solution offering, Rianta delivers to your custom specification. Using existing IP cores, we will design the top level and additional custom blocks, delivering a fully verified FPGA or ASIC solution. We provide handoff options of RTL, netlist or GDSII, and complete software drivers.