Hiring Location(s): Ottawa, Toronto

We are looking for self-motivated individuals with an in-depth understanding and hands on experience with verification architectures and HDL/logical design methodologies.

Responsibilities include:

  • Development of verification and test infrastructure for highly complex ASIC and SoC designs using the latest simulation and debugging tools
  • Application of constrained random verification techniques and Universal Verification methodology in order to achieve design verification objectives
  • Development and execution of ASIC verification Testplans
  • Creation and maintenance of automated regression infrastructure
  • Working with our external customers and/or internal IP designers to verify and validate their designs

Qualifications:

  • Experience in directed and constrained random verification techniques
  • Experience in development of test plans and test benches in OVM/UVM/VMM using System Verilog
  • Coverage analysis methodology

Desired Knowledge and Experience

  • Verilog, Specman e, Perl, C/C++
  • Hands on experience with OVM/UVM, VMM, and/or RVM/Vera simulation environments
  • Knowledge in one or more areas of the following would be a plus:
    • computer and peripheral architectures
    • video processing
    • deep learning
    • networking and processor protocols – Ethernet, PCIe, Interlaken, SATA, USB, DDR, security